1. Field of the Invention
This invention relates to computer systems and more particularly to instruction handling in computer systems and still more particularly to the I phase of instruction handling.
The invention finds particular utility in computer systems where the instruction set includes complex instructions which are not directly executable by the computer hardware. These complex instructions are sometimes referred to as "soft" instructions because they are not directly executable. The complex instructions are executed by executing sequences of simple instructions which are executable by the hardware. The present invention serves to eliminate certain sequences of simple instructions necessary to execute the complex instructions.
2. Description of the Prior Art
The prior art, such as set forth in the IBM Technical Disclosure Bulletin Vol 7, No. 4, September 1964, Page 289, teaches the concept of utilizing a single instruction to replace a sequence of instructions that a simulator would use to access and update the simulator instruction counter, to convert the address format of the simulator machine to the address format of the simulating machine, to fetch the next instruction of the simulated program, to perform any indexing required for the simulated instruction, to convert the address portion of the simulated instruction to an address format of the simulating machine for obtaining an operand and interpreting the simulated instruction operation code to cause a branch to the appropriate instruction routine of the simulating machine to execute the instruction.
The prior art also teaches a computer control arrangement where non-directly executable instructions are executed by a sequence of directly executable instructions. Such prior art is represented by IBM Technical Disclosure Bulletin, Vol 14, No. 1, June 1971, Page 298. Hence, the concept of extending the apparent hardware instruction set of a computer by simulating complex instructions with sequences of simple, directly executable instructions is known. The use of special instructions and hardware for interpretation of the complex or non-directly executable instructions is also known to the extent for dividing the simulated instruction into its constituent parts in a form interpretable by a simulating program.
The prior art does not teach an arrangement of invoking a single, special, directly executable instruction to compute operand addresses for operands of a non-directly executable instruction utilizing the same hardware used for computing operand addresses for directly executable instructions. Heretofore it has been the practice to use sequences of directly executable instructions to compute the operand addresses of operands for non-directly executable instructions or special purpose hardware was used. The use of sequences of directly executable instructions degrades performance and is not desireable. The use of special purpose hardware, of course, entails additional expense and is a more complex arrangement than the present invention. The principal objects of the invention are to provide improved apparatus for computing operand addresses for fetching operands of non-directly executable instructions which:
a. utilizes the same hardware used for computing operand addresses for directly executable instructions,
b. is relatively inexpensive for the function performed, and
c. does not substantially degrade performance.
These objects are achieved by using a special directly executable instruction for calculating operand addresses of simulated instructions. The directly executable special instruction uses the same instruction fetch or I phase hardware as used by other directly executable instructions. The operand address specification fields of simulated instructions are gated through the same address generation circuitry as are the operand address specification fields of directly executable instructions. The non-directly executable instructions are assigned operation code values from the same sequence as directly executable instructions. The number of operands in simulated instruction is determined by the same logic circuitry as for directly executable instructions.